1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers having distributed memories for storing test vector sequences for controlling actions at IC terminals during a test, and in particular to a system for reducing the number of vectors that must be stored in each memory to control a test.
2. Description of Related Art
An integrated circuit tester applies patterns of logic signals to input terminals of an integrated circuit (IC) and acquires the resulting output logic signal patterns produced at its output terminals. Testers typically include a separate "pin electronics" circuit for each IC terminal which, during each cycle of a test, can either send a high or low logic level test signal to the pin, sample an IC output signal at the pin and store data indicating its logic level, or do nothing. The action each pin electronics circuit takes during each test cycle is controlled by the value of input data (a "test vector") supplied thereto at the start of the cycle. A test vector may also include timing data that tells a pin electronic circuit when to carry out the action during the test cycle.
Early IC testers employed a central addressable memory for storing vectors needed during a test. The vector memory stored a large word at each address, each word being formed by all of the vector data needed for every pin electronics circuit for a particular test cycle. Thus, for example, if an IC had 8 terminals and a tester employed 8-bit vector data words, a 64-bit word was stored at each vector memory address. During the test, the vector memory was sequentially addressed so that it read out a next word during each test cycle. The eight vectors contained in the read out word were concurrently distributed to the pin electronics circuits by a large star bus.
As the size and complexity of IC's increased, so too did the number of terminals on an IC. Modern IC's can have hundreds of pins. Since a tester capable of testing such an IC requires a large number of pin electronics circuits, the use of a centralized vector memory has become impractical due to the large number of parallel buses needed to transmit the vectors concurrently to the pin electronics.
U.S. Pat. No. 4,862,067 issued Aug. 29, 1989 to Brune et al describes an integrated circuit tester employing a central address generator and a set of tester nodes, one node for each terminal of a device under test (DUT). Each node includes a memory for storing a sequence of test vectors, one for each cycle of the test. During a test the central address generator successively increments the address of the test vector memories of all nodes prior to the start of each test cycle so that each test vector memory reads out a new test vector and delivers it to the node's pin electronics at the beginning of each test cycle. In Brune's IC tester, all vector memories are linked to the host computer via a common bus through which the host computer loads vectors into the vector memories before the test. Thus the prior art multiplicity of vector buses leading from a central vector memory to all tester nodes is replaced by a single computer bus linking a host computer to distributed vector memories.
While this system reduces the amount of wiring in a tester, in many cases the number of vectors that must be distributed to the vector memories is so enormous that band width limitations on the computer bus greatly limit the speed with which an IC tester can be programmed for a test.
There have been attempts to reduce the amount of time required to transmit data to the node memories by changing the way the data defines the actions each node is to take during a test. U.S. Pat. No. 4,931,723 issued Jun. 5, 1990 to Jeffrey et al describes an IC tester having distributed vector memories which store data sequences formed by a set of test vectors separated by timing bits. As in Brune's system, each vector represents an action that the pin electronics is to take during a particular test cycle. However the timing bits preceding each vector indicates a number of test cycles that the system is to wait before sending the vector to the pin electronics. Each node includes a processor that reads a vector/time combination out of memory, waits the indicated number of test cycles and then sends the vector to the pin electronics. In the meantime, the processor simply repeats its last output vector.
While Jeffrey's system stores timing data as well as vector data in the memories, Jeffrey's system usually requires less total data to be sent to the vector memories than Brune's system. Brune's vector memories each store a test vector for each cycle of the test; Jeffrey's vector memories store a vector only for those test cycles in which a each state change is to occur in the pin electronics. For those test cycles in which no change is to occur, Jeffrey's vector memories need store only a single bit. In many integrated circuit tests, pin electronics often repeat the same action for many test cycles.
Jeffrey's system goes one step further in reducing the amount of data sent to the nodes by including loop instructions in the data sequence stored in the vector memories. Many IC tests require that a pattern of vectors be applied to the pin electronics of a node many times in succession. For example a node may be repeatedly driven high for 10 test cycles then low for 10 cycles. Jeffrey's loop instruction indicates the memory addresses of the first and last vectors of a sequence to be repeated and a number of times the sequence is to be repeated. When Jeffrey's node processor encounters a loop instruction, it stores the instruction in a register. Thereafter when the node processor reaches the first address of the loop, the node processor continues to read out and process the vector/time data in the normal manner to supply a pattern of vectors to the pin electronics. However at the same time, the node processor also stores the loop data in a cache memory. Upon reaching the last address of the loop data, the node processor begins reading and processing loop data from the cache memory instead of out of the main vector memory. The node processor continues to cycle through the cached loop data until it has processed the number of loops indicated by the loop instruction.
One might think that storing the loop in the cache memory is unnecessary because the Jeffrey et al system could simply reread the loop from the main vector memory. However since the node processor must supply a vector to the pin electronics during each test cycle, a loop instruction inserted into the sequence of test vectors could cause a lapse in the stream of vectors flowing to the pin electronics. In Jeffrey's system, the first loop instruction is delivered to the node before the test starts. Each subsequent loop instruction appears at the end of a preceding loop. Since on the second pass through the loop, the processor obtains vectors from the cache and not from the vector memory, the processor is free to obtain and process a next loop instruction from the vector memory at the same time. Thus the purpose of the cache is to provide an alternate vector data source while the processor is accessing the vector memory to obtain the next loop instruction.
While Jeffrey's system reduces the amount of vector data that must be distributed to the nodes, a separate set of instructions and timing data must be created and supplied to each node before the test. With the instructions and timing data co-mingled.
What is needed is an IC tester that reduces the amount of data that must be distributed to the nodes before a test without having to distribute instructions to the nodes before the test.